// (C) 2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`timescale 1ns / 1ps

module scmfpga_top
(
input        CLK_25M_OSC_SCM_FPGA,              // IO2_K6, From crystal oscillator chip, external 25M clock for FPGA usage
input        PWRGD_P1V2_MAX10_AUX_SCM_PLD_R,    // IO2_J6, From FPGA P1V2 VR, indicate FPGA power supply is OK, as external reset signal for FPGA
// LVDS Link to CPU FPGA
input        LVDS_CLK_RX_DP,
output       LVDS_CLK_TX_R_DP,
input        LVDS_RX_DP,
output       LVDS_TX_R_DP,

inout        SMB_CPLD_UPDATE_STBY_LVC3_SCL,    //I2C_PFR_SCL
inout        SMB_CPLD_UPDATE_STBY_LVC3_SDA,    //I2C_PFR_SDA

inout        SMB_LVDS_MM_SCL,                  //I2C_BMC_SCL
inout        SMB_LVDS_MM_SDA,                  //I2C_BMC_SDA
//UART to BMC
output reg   UART_BMC_TXD,
output reg   UART_BMC_RTS,
input        UART_BMC_RXD,
input        UART_BMC_CTS,

//sGPIO to BMC
input         SGPIO_BMC_CLK,
input         SGPIO_BMC_DOUT,
output        SGPIO_BMC_DIN_R,
input         SGPIO_BMC_LD_N, 
//sGPIO to PFR
input         SGPIO_PFR_CLK,
input         SGPIO_PFR_DOUT,
output        SGPIO_PFR_DIN_R,
input         SGPIO_PFR_LD_N, 

//*********Following Ports for Platform Logic*****************
//SMB
inout       SMB_CHASSIS_SENSOR_STBY_LVC3_SCL,
inout       SMB_CHASSIS_SENSOR_STBY_LVC3_SDA,
inout       SMB_PMBUS2_STBY_LVC3_SCL,
inout       SMB_PMBUS2_STBY_LVC3_SDA,
inout       SMB_TEMPSENSOR_STBY_LVC3_SCL,
inout       SMB_TEMPSENSOR_STBY_LVC3_SDA,
inout       SMB_PMBUS1_STBY_LVC3_SCL,
inout       SMB_PMBUS1_STBY_LVC3_SDA,
inout       SMB_PIROM_LVC3_SCL,
inout       SMB_PIROM_LVC3_SDA,
//PWR SEQ
output      FM_BMC_VR_EN,
output      FM_P5V_MAIN_SCM_EN,
input       PWRGD_P1V05_SCM_AUX,
input       PWRGD_P5V_MAIN_SCM,
input       PWRGD_P1V0_BMC_AUX,
output      RST_SRST_BMC_PFR_N,
input       RST_SRST_BMC_SCM_FPGA_N,    
//PLT Logic
input       RST_BMC_PCIE_MUX_N,
input       RST_BMC_HSBP_MUX_N,
output      FM_SLPS4_N,
output      FM_SLPS3_N,
output      PWRGD_CPU0_LVC3,
//output      PWRGD_CPU1_LVC3,
input       FM_BMC_ONCTL_N,
output      PWRGD_PS_PWROK_SCM_PLD_R,
output      RST_PLTRST_CPU0_LVC3_N,
output      RST_PLTRST_CPU1_LVC3_N,
input       RST_PLTRST_CPU0_PFR_LVC3_N,
input       RST_PLTRST_CPU1_PFR_LVC3_N,
output      FM_PWRGD_AUX_PWRGD_CPU0,            // To PFR, indicate CPU0 VCCFA_EHV and VNN power rails are fully on, can release CPU_AUX_PWRGD
output      FM_PWRGD_AUX_PWRGD_CPU1,            // To PFR, indicate CPU1 VCCFA_EHV and VNN power rails are fully on, can release CPU1 AUX_PWRGD
input       PWRGD_AUX_PWRGD_CPU0,               // From PFR, indicate CPU0 IFWI SPI flash verified
input       PWRGD_AUX_PWRGD_CPU1,               // From PFR, indicate CPU1 IFWI SPI flash verified
output      FP_BMC_PWR_BTN_N,
input       FP_BMC_PWR_BTN_OUT_N,
output      FP_RST_BTN_N,

input       RST_BMC_RSTBTN_OUT_N,
input       RST_PFR_RTCRST_CPU0_N,
input       RST_PFR_RTCRST_CPU1_N,
input       RST_RTCRST_TTK3_N,
output      FP_ID_BTN_N,
output      FP_NMI_BTN_N,
input       FM_BMC_BMCINIT,
output      NVME_LVC3_ALERT_N,
input       FP_ID_LED_N,
input       FP_LED_STATUS_AMBER_N,
input       FP_LED_STATUS_GREEN_N,
output      FM_FORCE_BMC_UPDATE_CONTROL,
input       SPEAKER_BMC,
input       PARTITION_DEBUG_SEL,
output      PARTITION_DEBUG_SEL_OUT,
input       RST_DEDI_BUSY_CPU0_N,
input       RST_DEDI_BUSY_CPU1_N,
output      FM_HPFR_IN,
output      FM_LEGACY,
output      FM_HPFR_ACTIVE,
input       FM_HPFR_OUT,
output      FM_BMC_SAFS_SEL,
input       FM_CK440_REMOTESSC_GPIO0,
input       FM_CK440_REMOTESSC_GPIO1,
input       FM_USB_OC1_N,
input       FM_BMC_TRUST_N,
input       FM_P1_BMC_PWRBTN_OUT_N,
input       RST_P1_BMC_RSTBTN_OUT_N,
//Error Handling
output      IRQ_PMBUS_ALERT_N,
output      FM_PLT_BMC_THERMTRIP_N,
output      H_CPU0_CATERR_RMCA_LVC3_N,
output      H_CPU1_CATERR_RMCA_LVC3_N,
output      H_CPU0_ERR0_LVC3_N,
output      H_CPU0_ERR1_LVC3_N,
output      H_CPU0_ERR2_LVC3_N,
output      FM_CPU1_ERR0_LVT3_N,
output      FM_CPU1_ERR1_LVT3_N,
output      FM_CPU1_ERR2_LVT3_N,
//PFR interaction RSVD
output      PFR_CC_RSVD_0,
output      PFR_CC_RSVD_1,
input       PFR_CC_RSVD_2,
input       PFR_CC_RSVD_3,
input       PFR_CC_RSVD_4,        
//DC-SCM
output      HPM_STBY_EN,
input       HPM_STBY_RDY,
output      HPM_STBY_RST_N,    
//PLT LOGIC
input       BMC_CMOS_CLEAR_N,
output      FM_STANDALONE_MODE_N,
output      FM_4S_8S_MODE_N,
output      FM_NODE_ID0,
output      FM_NODE_ID1,
input       FM_SKT0_FAULT_LED,
input       FM_SKT1_FAULT_LED,
input       FM_CPU_FBRK_DEBUG_N,
output      DBG_GPIO_POD_PRSNT_N,
output      DBG_GPIO_JUMPER_EN_DET,
input       FM_SPD_SWITCH_CTRL_N,
input       FM_TPM_EN_PULSE,
output      PWRGD_AUX_PWRGD_BMC_CPU0,
input       FM_LED_BMC_CPU_RSTIND,         
input       A_P3V_BAT_SCALED_EN,
output      FM_DUAL_PARTITION_R_N,
output      FM_PARTITION_SEL_R,
output      FM_BIOS_IMAGE_SWAP_N,
inout       PFR_DEBUG_JUMPER_RJC_N,
inout       PFR_FORCE_RECOVERY_RJC_N,
inout       FM_TTK_SPI_EN_RJC_N,
output      FM_VOLTAGE_TRANSLATOR_EN 
);

//************* Internal Wires ******************
wire         clk_2m;        
wire         clk_20m;           
wire         clk_100m;      
wire         scm_pll_locked;
wire         Reset_2m_N;
wire         Reset_100m_N;
wire         Reset_sGPIO_BMC_N;
wire         Reset_sGPIO_PFR_N;
//i2c_slave for BMC
wire         i2c_bmc_data_in; 
wire         i2c_bmc_clk_in;  
wire         i2c_bmc_data_oe; 
wire         i2c_bmc_clk_oe;
//avmm intf from I2C slave 
wire [31: 0] avmm_bmc_addr;   
wire         avmm_bmc_read;   
wire [31: 0] avmm_bmc_rdata;  
wire         avmm_bmc_rdvalid;
wire         avmm_bmc_waitrq;
wire         avmm_bmc_write;   
wire [ 3: 0] avmm_bmc_byteen; 
wire [31: 0] avmm_bmc_wdata;
//avmm connected to scm local csr
wire [31: 0] scm_csr_address;      
wire         scm_csr_write;        
wire [31: 0] scm_csr_writedata;    
wire         scm_csr_read;         
wire [31: 0] scm_csr_readdata;     
wire         scm_csr_readdatavalid;
wire         scm_csr_waitrequest;  
wire [ 3: 0] scm_csr_byteenable;
//avmm connected between i2c & rsu
wire [31: 0] avmm_rsu_address;      
wire         avmm_rsu_write;        
wire [31: 0] avmm_rsu_writedata;    
wire         avmm_rsu_read;         
wire [31: 0] avmm_rsu_readdata;     
wire         avmm_rsu_readdatavalid;
//avmm connected to scm pfr csr
wire [31: 0] scm_pfr_csr_address;      
wire         scm_pfr_csr_write;        
wire [31: 0] scm_pfr_csr_writedata;    
wire         scm_pfr_csr_read;         
wire [31: 0] scm_pfr_csr_readdata;     
wire         scm_pfr_csr_readdatavalid;
wire         scm_pfr_csr_waitrequest;  
wire [ 3: 0] scm_pfr_csr_byteenable;
//avmm connected to general csr
wire [31: 0] general_csr_address;      
wire         general_csr_write;        
wire [31: 0] general_csr_writedata;    
wire         general_csr_read;         
wire [31: 0] general_csr_readdata;     
wire         general_csr_readdatavalid;
wire         general_csr_waitrequest;  
wire [ 3: 0] general_csr_byteenable;
//avmm connected to MCSI which crosses serial link
wire [31: 0] mcsi_address;      
wire         mcsi_write;        
wire [31: 0] mcsi_writedata;    
wire         mcsi_read;         
wire [31: 0] mcsi_readdata;     
wire         mcsi_readdatavalid;
wire         mcsi_waitrequest;  
wire [ 3: 0] mcsi_byteenable; 
//avmm connected to mcsi internal csr
wire [31: 0] mcsi_csr_address;      
wire         mcsi_csr_write;        
wire [31: 0] mcsi_csr_writedata;    
wire         mcsi_csr_read;         
wire [31: 0] mcsi_csr_readdata;     
wire         mcsi_csr_readdatavalid;
wire         mcsi_csr_waitrequest;  
wire [ 3: 0] mcsi_csr_byteenable;    
//i2c intf from i2c_slave for PFR  
wire         i2c_pfr_data_oe; 
//ioc lvds
wire          tx_coreclock;
wire          tx_pll_locked;
wire [ 13: 0] scl_rsv;
wire [ 13: 0] sda_rsv;
wire [111: 0] gpio_out_rsv;
wire [111: 0] gpio_in;
wire [111: 0] gpio_out;
wire [  1: 0] uart_txd;
wire [  1: 0] uart_rts;
wire          uart_source_select;
wire          bmc_force_update_sel;
wire          mcsi_aligned;
wire          Reset_N;
//wire [111:0]  normal_gpio_rst_value;
//flash avmm intf
wire          flash_csr_addr;          
wire          flash_csr_read;           
wire [31: 0]  flash_csr_writedata;      
wire          flash_csr_write;          
wire [31: 0]  flash_csr_readdata;      
wire [31: 0]  flash_data_addr;          
wire          flash_data_read;          
wire [31: 0]  flash_data_writedata;     
wire          flash_data_write;         
wire [31: 0]  flash_data_readdata;      
wire          flash_data_waitrequest;   
wire          flash_data_readdatavalid; 
wire [ 6: 0]  flash_data_burstcount;
//pfr i2c_slave avmm intf
wire [15: 0]  avmm_pfr_address;   
wire [15: 0]  avmm_pfr_writedata; 
wire          avmm_pfr_write;     
wire          avmm_pfr_read; 
wire          avmm_pfr_readvalid;
wire [15: 0]  avmm_pfr_readdata; 
wire [15: 0]  avmm_pfr_readdata_h;   
//IIC_MM access error report
wire [3:0]    status_reg_mm;          //LVDS_MM channel error log
wire [3:0]    status_reg;             //Final error log to general csr
wire          invalid_access_scm_mcsi; 
wire          invalid_access_scm_glb;
wire          invalid_access_general;
//IIC slave error report to RSU
wire           I2C_CRC_Error;
   
//************* Internal Registers **************
reg  [  1: 0] uart_rxd;
reg  [  1: 0] uart_cts;
reg           i2c_pfr_data_in; 
reg           i2c_pfr_clk_in; 
reg           i2c_pfr_data_sync; 
reg           i2c_pfr_clk_sync; 

//************* Platform Logic Internal Wires ******************
wire     wRST_BMC_RSTBTN_OUT_N;
wire     wRST_BMC_PCIE_MUX_N;
wire     wRST_BMC_HSBP_MUX_N;
wire     wFM_BMC_ONCTL_N;
wire     wFP_BMC_PWR_BTN_OUT_N;
wire     wFM_BMC_BMCINIT;
wire     wFP_ID_LED_N;
wire     wFP_LED_STATUS_AMBER_N;
wire     wFP_LED_STATUS_GREEN_N;
wire     wSPEAKER_BMC;
wire     wFM_SKT0_FAULT_LED;
wire     wFM_SKT1_FAULT_LED;
wire     wFM_CPU_FBRK_DEBUG_N;
wire     wFM_SPD_SWITCH_CTRL_N;
wire     wFM_TPM_EN_PULSE;
wire     wFM_LED_BMC_CPU_RSTIND;
wire     wA_P3V_BAT_SCALED_EN;    
wire     wP5V_MAIN_PWR_FAULT;
wire     wFM_CK440_REMOTESSC_GPIO0;
wire     wFM_CK440_REMOTESSC_GPIO1;

//Signals be used  both inside dcscm_main.v module and pss thru to LVDS
wire     wRST_RTC_RST_CPU1;           //Internal logic generate; tunnel to LVDS
wire     wRST_RTC_RST_CPU0;           //Internal logic generate; tunnel to LVDS
wire     wSCM_BMC_AUX_PWR_FAULT;      //Internal logic generate; tunnel to LVDS
wire     wSCM_PWR_FAULT;              //Internal logic generate; tunnel to LVDS
wire     wBMC_PWR_FAULT;              //Internal logic generate; tunnel to LVDS
wire     wRST_PLTRST_CPU0_PFR_LVC3_N; //GlitchFilter'ed; signal used both by internal module and tunnel to LVDS
wire     wRST_PLTRST_CPU1_PFR_LVC3_N; //GlitchFilter'ed; signal used both by internal module and tunnel to LVDS
wire     wPWRGD_AUX_PWRGD_CPU0;       //GlitchFilter'ed; signal used both by internal module and tunnel to LVDS
wire     wPWRGD_AUX_PWRGD_CPU1;       //GlitchFilter'ed; signal used both by internal module and tunnel to LVDS
wire     wFM_DUAL_PARTITION_R_N;      //GlitchFilter'ed; signal used both by internal module and tunnel to LVDS
wire     wFM_PARTITION_SEL_R;         //GlitchFilter'ed; signal used both by internal module and tunnel to LVDS

//BIOS PostCode
wire     wBIOS_POST_CODE_LED_0;
wire     wBIOS_POST_CODE_LED_1;
wire     wBIOS_POST_CODE_LED_2;
wire     wBIOS_POST_CODE_LED_3;
wire     wBIOS_POST_CODE_LED_4;
wire     wBIOS_POST_CODE_LED_5;
wire     wBIOS_POST_CODE_LED_6;
wire     wBIOS_POST_CODE_LED_7;

//PFR PostCode
wire    wPFR_POST_CODE_LED_0;
wire    wPFR_POST_CODE_LED_1;
wire    wPFR_POST_CODE_LED_2;
wire    wPFR_POST_CODE_LED_3;
wire    wPFR_POST_CODE_LED_4;
wire    wPFR_POST_CODE_LED_5;
wire    wPFR_POST_CODE_LED_6;
wire    wPFR_POST_CODE_LED_7;

//LVDS
wire        wFM_SERIAL_BOOT              ;
wire        wFM_BOARD_SKU_ID5            ;
wire        wFM_SLPS4_CPU1_CPU_PLD_N     ;
wire        wFM_SLPS3_CPU1_CPU_PLD_N     ;
wire        wFM_CPU0_PKGID0              ;
wire        wFM_CPU0_PKGID1              ;
wire        wFM_CPU0_PKGID2              ;
wire        wFM_CPU0_PROC_ID0            ;
wire        wFM_CPU0_PROC_ID1            ;
wire        wFM_CPU0_SKTOCC_LVT3_PLD_N   ;
wire        wFM_CPU1_PKGID0              ;
wire        wFM_CPU1_PKGID1              ;
wire        wFM_CPU1_PKGID2              ;
wire        wFM_CPU1_PROC_ID0            ;
wire        wFM_CPU1_PROC_ID1            ;
wire        wFM_CPU1_SKTOCC_LVT3_PLD_N   ;
wire        wRST_BMC_SRST_DIO_N          ;
wire        wFM_BOARD_SKU_ID0            ;
wire        wFM_BOARD_SKU_ID1            ;
wire        wFM_BOARD_SKU_ID2            ;
wire        wFM_BOARD_SKU_ID3            ;
wire        wFM_BOARD_SKU_ID4            ;
wire        wFM_BOARD_REV_ID0            ;
wire        wFM_BOARD_REV_ID1            ;
wire        wFM_BOARD_REV_ID2            ;
wire        wIRQ_CPU0_VRHOT_N            ;
wire        wIRQ_CPU1_VRHOT_N            ;
wire        wIRQ_CPU0_MEM_VRHOT_N        ;
wire        wIRQ_CPU1_MEM_VRHOT_N        ;
wire        wFM_S3M_CPU0_CPLD_CRC_ERROR  ;
wire        wFM_S3M_CPU1_CPLD_CRC_ERROR  ;
wire  [1:0] wH_CPU0_CATERR_LVC1_ENCODE   ;
wire  [1:0] wH_CPU0_RMCA_LVC1_ENCODE     ;
wire  [1:0] wH_CPU1_CATERR_LVC1_ENCODE   ;
wire  [1:0] wH_CPU1_RMCA_LVC1_ENCODE     ;
wire        wH_CPU0_THERMTRIP_LVC1_N     ;
wire        wH_CPU0_MEMTRIP_LVC1_N       ;
wire        wH_CPU0_MEMHOT_OUT_LVC1_N    ;
wire        wH_CPU0_MON_FAIL_PLD_LVC1_N  ;
wire        wH_CPU1_THERMTRIP_LVC1_N     ;
wire        wH_CPU1_MEMTRIP_LVC1_N       ;
wire        wH_CPU1_MEMHOT_OUT_LVC1_N    ;
wire        wH_CPU0_ERR0_LVC1_N          ;
wire        wH_CPU0_ERR1_LVC1_N          ;
wire        wH_CPU0_ERR2_LVC1_N          ;
wire        wH_CPU1_ERR0_LVT1_N          ;
wire        wH_CPU1_ERR1_LVT1_N          ;
wire        wH_CPU1_ERR2_LVT1_N          ;
wire        wH_CPU1_MON_FAIL_PLD_LVC1_N  ;
reg         pwrgd_ps_pwrok_meta;
reg         pwrgd_ps_pwrok_sync;
wire  [7:0] wLED_CPU0_DIMM_CH1_8_FLT;
wire  [3:0] wLED_CPU0_DIMM_CH9_12_FLT;
wire  [7:0] wLED_CPU1_DIMM_CH1_8_FLT;
wire  [3:0] wLED_CPU1_DIMM_CH9_12_FLT;
wire        GPIO_RSVD_46;
wire        GPIO_RSVD_47;
wire        wPWRGD_CPU0_LVC3;
wire        wSCM_CPLD_UPDATE_HIDE;
wire        wCPU1_AUX_PWR_OK;
//RJC signals
wire  FM_TTK_SPI_EN_RJC_N_IN;
wire  PFR_DEBUG_JUMPER_RJC_N_IN;
wire  PFR_FORCE_RECOVERY_RJC_N_IN;


wire   FM_TTK_SPI_EN_RJC_N_Override        ;
wire   PFR_DEBUG_JUMPER_RJC_N_Override     ;
wire   PFR_FORCE_RECOVERY_RJC_N_Override   ;
wire   FM_TTK_SPI_EN_RJC_N_Value           ;
wire   PFR_DEBUG_JUMPER_RJC_N_Value        ;
wire   PFR_FORCE_RECOVERY_RJC_N_Value      ;


//sGPIO related signals
 wire        wLED_POSTCODE_0;
 wire        wLED_POSTCODE_1;
 wire        wLED_POSTCODE_2;
 wire        wLED_POSTCODE_3;
 wire        wLED_POSTCODE_4;
 wire        wLED_POSTCODE_5;
 wire        wLED_POSTCODE_6;
 wire        wLED_POSTCODE_7;
 wire        wLED_CPU0_CHA_DIMM1_FAULT;
 wire        wLED_CPU0_CHA_DIMM2_FAULT;
 wire        wLED_CPU0_CHB_DIMM1_FAULT;
 wire        wLED_CPU0_CHB_DIMM2_FAULT;
 wire        wLED_CPU0_CHC_DIMM1_FAULT;
 wire        wLED_CPU0_CHC_DIMM2_FAULT;
 wire        wLED_CPU0_CHD_DIMM1_FAULT;
 wire        wLED_CPU0_CHD_DIMM2_FAULT;
 wire        wLED_CPU0_CHE_DIMM1_FAULT;
 wire        wLED_CPU0_CHE_DIMM2_FAULT;
 wire        wLED_CPU0_CHF_DIMM1_FAULT;
 wire        wLED_CPU0_CHF_DIMM2_FAULT;

 wire        wLED_CPU1_CHA_DIMM1_FAULT;
 wire        wLED_CPU1_CHA_DIMM2_FAULT;
 wire        wLED_CPU1_CHB_DIMM1_FAULT;
 wire        wLED_CPU1_CHB_DIMM2_FAULT;
 wire        wLED_CPU1_CHC_DIMM1_FAULT;
 wire        wLED_CPU1_CHC_DIMM2_FAULT;
 wire        wLED_CPU1_CHD_DIMM1_FAULT;
 wire        wLED_CPU1_CHD_DIMM2_FAULT;
 wire        wLED_CPU1_CHE_DIMM1_FAULT;
 wire        wLED_CPU1_CHE_DIMM2_FAULT;
 wire        wLED_CPU1_CHF_DIMM1_FAULT;
 wire        wLED_CPU1_CHF_DIMM2_FAULT;
								 
 wire        wLED_CPU0_CHG_DIMM1_FAULT;
 wire        wLED_CPU0_CHG_DIMM2_FAULT;
 wire        wLED_CPU0_CHH_DIMM1_FAULT;
 wire        wLED_CPU0_CHH_DIMM2_FAULT;
 wire        wLED_CPU1_CHG_DIMM1_FAULT;
 wire        wLED_CPU1_CHG_DIMM2_FAULT;
 wire        wLED_CPU1_CHH_DIMM1_FAULT;
 wire        wLED_CPU1_CHH_DIMM2_FAULT;
 wire        wLED_CPU0_CHI_DIMM1_FAULT;
 wire        wLED_CPU0_CHI_DIMM2_FAULT;
 wire        wLED_CPU0_CHJ_DIMM1_FAULT;
 wire        wLED_CPU0_CHJ_DIMM2_FAULT;
 wire        wLED_CPU0_CHK_DIMM1_FAULT;
 wire        wLED_CPU0_CHK_DIMM2_FAULT;
 wire        wLED_CPU0_CHL_DIMM1_FAULT;
 wire        wLED_CPU0_CHL_DIMM2_FAULT;
 wire        wLED_CPU1_CHI_DIMM1_FAULT;
 wire        wLED_CPU1_CHI_DIMM2_FAULT;
 wire        wLED_CPU1_CHJ_DIMM1_FAULT;
 wire        wLED_CPU1_CHJ_DIMM2_FAULT;
 wire        wLED_CPU1_CHK_DIMM1_FAULT;
 wire        wLED_CPU1_CHK_DIMM2_FAULT;
 wire        wLED_CPU1_CHL_DIMM1_FAULT;
 wire        wLED_CPU1_CHL_DIMM2_FAULT;
 wire        wCPU_MISMATCH;
 wire        wMEM_PWR_FLT;
 wire        wCPU_PWR_FLT;
 wire        wPSU_PWR_FLT;
 wire        wP3V3_FAULT;
 wire        wCPU_AUX_PWR_FLT;
 wire        wFM_VAL_DBG_JUMPER_EN;
 wire        wSURPRISE_RESET;
 wire        wFM_CPU1_INTR_CLK_CONFDONE;
 wire        wFM_GLOBAL_RESET;
 wire        wFM_BMC_INIT_DONE;
 wire        wPWRGD_S0_PWROK_CPU0;
 wire  [3:0] wReserved_0;
 wire  [3:0] wReserved_1;
 wire  [23:0] wReserved_2;
 wire  [7:0] wReserved_3;
 wire  [6:0] wPFR_RSVD_15_9;
 wire        wFM_1200VA_OC;
 wire  [7:0] wSCMFPGAREV;
 wire  [7:0] wSCMFPGATEST;
 
//This pll gets external clock source from SCM board
pll_scm pll_scm_inst (
    .areset ( !PWRGD_P1V2_MAX10_AUX_SCM_PLD_R ),
    .inclk0 ( CLK_25M_OSC_SCM_FPGA            ),
    .c0     ( clk_2m                          ),
    .c1     ( clk_20m                         ),
    .c2     ( clk_100m                        ),
    .locked ( scm_pll_locked                  )
);

//Reset Generator
rst_gen rst_gen_2m
(
   .rst_n      ( Reset_N    ),          //Async reset

   .clk        ( clk_2m     ),

   .rst_sync_n ( Reset_2m_N )

);

rst_gen rst_gen_100m
(
   .rst_n      ( Reset_N      ),        //Async reset

   .clk        ( clk_100m     ),

   .rst_sync_n ( Reset_100m_N )

);

rst_gen rst_gen_sgpio_bmc
(
   .rst_n      ( Reset_N           ),        //Async reset

   .clk        ( SGPIO_BMC_CLK     ),

   .rst_sync_n ( Reset_sGPIO_BMC_N )

);

rst_gen rst_gen_sgpio_pfr
(
   .rst_n      ( Reset_N           ),        //Async reset

   .clk        ( SGPIO_PFR_CLK     ),

   .rst_sync_n ( Reset_sGPIO_PFR_N )

);

//Sample I2C values and synchronize into our domain
always @( posedge clk_20m )
begin
  if(~Reset_N)
    begin
      i2c_pfr_clk_sync   <= 1'b0;
      i2c_pfr_data_sync  <= 1'b0;
      i2c_pfr_clk_in     <= 1'b0;
      i2c_pfr_data_in    <= 1'b0;
    end
  else
    begin
      i2c_pfr_clk_sync  <= SMB_CPLD_UPDATE_STBY_LVC3_SCL;
      i2c_pfr_data_sync <= SMB_CPLD_UPDATE_STBY_LVC3_SDA;
      i2c_pfr_clk_in    <= i2c_pfr_clk_sync;
      i2c_pfr_data_in   <= i2c_pfr_data_sync;
    end
end

// Synchronize to 2M domain
always @( posedge clk_2m )
begin
  if(~Reset_2m_N)
    begin

      pwrgd_ps_pwrok_meta <= 1'b0;
      pwrgd_ps_pwrok_sync <= 1'b0;
    end
  else
    begin
      pwrgd_ps_pwrok_meta <= PWRGD_PS_PWROK_SCM_PLD_R;
      pwrgd_ps_pwrok_sync <= pwrgd_ps_pwrok_meta;
    end
end

assign SMB_CPLD_UPDATE_STBY_LVC3_SDA = i2c_pfr_data_oe ? 1'bz : 1'b0;
//This i2c_slave is connected to PFR
i2c_slv i2c_slave_pfr
(
    .Clock                   ( clk_20m            ),
    .Reset                   ( ~Reset_N           ),
    .SclIn                   ( i2c_pfr_clk_in     ),
    .SdaIn                   ( i2c_pfr_data_in    ),
    .SdaOut                  ( i2c_pfr_data_oe    ),
    .DeviceAddress           ( 8'h5A              ),
    //avmm_intf                
    .avmm_address            ( avmm_pfr_address   ),            
    .avmm_writedata          ( avmm_pfr_writedata ),          
    .avmm_write              ( avmm_pfr_write     ),              
    .avmm_read               ( avmm_pfr_read      ),               
    .avmm_readvalid          ( avmm_pfr_readvalid ),
    .avmm_readdata           ( avmm_pfr_readdata  ),
	 .I2C_CRC_Error           ( I2C_CRC_Error      )
);  
//Master is i2c_slave from PFR, slv1 is RSU and slv2 is scm_pfr_csr
avmm_mux_1to2 
  #(
    .SLV1_ADDR_LOW  ( 32'h0000 ),
    .SLV1_ADDR_High ( 32'h1FFF ),
    .SLV2_ADDR_LOW  ( 32'h2100 ),
    .SLV2_ADDR_High ( 32'h21FF )   
   ) 
avmm_mux_1to2_inst 
(
    .clk                 ( clk_20m                     ),
    .rst_n               ( Reset_N                     ),	 
    //AVMM_Single_Master, connected to I2C slave AVMM
    .mst_address         ( {16'b0, avmm_pfr_address}   ),
    .mst_write           ( avmm_pfr_write              ),
    .mst_writedata       ( {16'b0, avmm_pfr_writedata} ),          
    .mst_read            ( avmm_pfr_read               ),          
    .mst_readdata        ( {avmm_pfr_readdata_h, avmm_pfr_readdata} ),      
    .mst_readdatavalid   ( avmm_pfr_readvalid          ), 
    .mst_waitrequest     (                             ),
    .mst_byteenable      (  4'b1111                    ),
    //AVMM_Slave_1, connect to rsu        
    .slv1_address        ( avmm_rsu_address            ),
    .slv1_write          ( avmm_rsu_write              ),
    .slv1_writedata      ( avmm_rsu_writedata          ),          
    .slv1_read           ( avmm_rsu_read               ),          
    .slv1_readdata       ( avmm_rsu_readdata           ),      
    .slv1_readdatavalid  ( avmm_rsu_readdatavalid      ), 
    .slv1_waitrequest    ( 1'b0                        ),
    .slv1_byteenable     (                             ),
    //AVMM_Slave_2, connect to scm pfr CSR     
    .slv2_address        ( scm_pfr_csr_address         ),
    .slv2_write          ( scm_pfr_csr_write           ),
    .slv2_writedata      ( scm_pfr_csr_writedata       ),          
    .slv2_read           ( scm_pfr_csr_read            ),          
    .slv2_readdata       ( scm_pfr_csr_readdata        ),      
    .slv2_readdatavalid  ( scm_pfr_csr_readdatavalid   ), 
    .slv2_waitrequest    ( scm_pfr_csr_waitrequest     ),            
    .slv2_byteenable     ( scm_pfr_csr_byteenable      )
);
//Store SCM PFR CSR for PFR CPLD to access
scm_pfr_csr scm_pfr_csr_inst
(
    .clk                ( clk_20m                   ),
    .reset              ( ~Reset_N                  ),
    //avmm interface                                
    .avmm_address       ( scm_pfr_csr_address       ),
    .avmm_write         ( scm_pfr_csr_write         ),
    .avmm_writedata     ( scm_pfr_csr_writedata     ),          
    .avmm_read          ( scm_pfr_csr_read          ),     
    .avmm_readdata      ( scm_pfr_csr_readdata      ),      
    .avmm_readdatavalid ( scm_pfr_csr_readdatavalid ), 
    .avmm_waitrequest   ( scm_pfr_csr_waitrequest   ),           
    .avmm_byteenable    ( scm_pfr_csr_byteenable    )
);

//Remote System Update
RSU_WRAPPER
    #(
      .FwRevision   ( 16'h10CF ),
      .DeviceAddr   ( 8'h5A    ),
      .DeviceType   ( 16'h11AD ),
      .SupportMode  ( 8'h06    )
     )
rsu_inst
(
    .Clock                   ( clk_20m                   ),
    .PllLocked               ( scm_pll_locked            ),
    .Reset_N                 ( Reset_N                   ),
    .LockPin                 ( 1'b0                      ),
	 .I2C_CRC_Error           ( I2C_CRC_Error             ),
    //i2C slave avmm intf
    .avmm_address            ( avmm_rsu_address[15:0]    ),            
    .avmm_writedata          ( avmm_rsu_writedata[15:0]  ),          
    .avmm_write              ( avmm_rsu_write            ),              
    .avmm_read               ( avmm_rsu_read             ),               
    .avmm_readvalid          ( avmm_rsu_readdatavalid    ),
    .avmm_readdata           ( avmm_rsu_readdata[15:0]   ),
    //flash avmm intf
    .avmm_csr_addr           ( flash_csr_addr            ),
    .avmm_csr_read           ( flash_csr_read            ),
    .avmm_csr_writedata      ( flash_csr_writedata       ),
    .avmm_csr_write          ( flash_csr_write           ),
    .avmm_csr_readdata       ( flash_csr_readdata        ),
    .avmm_data_addr          ( flash_data_addr           ),
    .avmm_data_read          ( flash_data_read           ),
    .avmm_data_writedata     ( flash_data_writedata      ),
    .avmm_data_write         ( flash_data_write          ),
    .avmm_data_readdata      ( flash_data_readdata       ),
    .avmm_data_waitrequest   ( flash_data_waitrequest    ),
    .avmm_data_readdatavalid ( flash_data_readdatavalid  ),
    .avmm_data_burstcount    ( flash_data_burstcount     )    
);

//Instantiate Internal Flash
scm_flash scm_flash_inst
(
    .clock                    ( clk_20m                  ),
    .reset_n                  ( Reset_N                  ),
    .avmm_csr_addr            ( flash_csr_addr           ),
    .avmm_csr_read            ( flash_csr_read           ),
    .avmm_csr_writedata       ( flash_csr_writedata      ),
    .avmm_csr_write           ( flash_csr_write          ),
    .avmm_csr_readdata        ( flash_csr_readdata       ),
    .avmm_data_addr           ( flash_data_addr[16:0]    ),
    .avmm_data_read           ( flash_data_read          ),
    .avmm_data_writedata      ( flash_data_writedata     ),
    .avmm_data_write          ( flash_data_write         ),
    .avmm_data_readdata       ( flash_data_readdata      ),
    .avmm_data_waitrequest    ( flash_data_waitrequest   ),
    .avmm_data_readdatavalid  ( flash_data_readdatavalid ),
    .avmm_data_burstcount     ( flash_data_burstcount    )  
);

//This i2c_slave is connected to BMC
assign i2c_bmc_data_in = SMB_LVDS_MM_SDA;
assign SMB_LVDS_MM_SDA = i2c_bmc_data_oe ? 1'b0 : 1'bz;
assign i2c_bmc_clk_in  = SMB_LVDS_MM_SCL;
assign SMB_LVDS_MM_SCL = i2c_bmc_clk_oe ? 1'b0 : 1'bz;

i2c_slave_bmc_wrapper i2c_slave_bmc_wrapper_scm_inst
(
   .clk                       ( tx_coreclock             ),
   .rst_n                     ( tx_pll_locked            ), 											

   //IIC interface
   .i2c_data_in               ( i2c_bmc_data_in          ),
   .i2c_clk_in                ( i2c_bmc_clk_in           ),
   .i2c_data_oe               ( i2c_bmc_data_oe          ),
   .i2c_clk_oe                ( i2c_bmc_clk_oe           ),
   
   //AVMM interface	
	.waitrequest               ( avmm_bmc_waitrq          ),
	.readdatavalid             ( avmm_bmc_rdvalid         ),
	.readdata                  ( avmm_bmc_rdata           ),
	
	.address                   ( avmm_bmc_addr            ),
	.write                     ( avmm_bmc_write           ),
	.writedata                 ( avmm_bmc_wdata           ),
	.read                      ( avmm_bmc_read            ),
	.byteenable                ( avmm_bmc_byteen          )
);


//UART channel over LVDS
always @ (*) begin
    if (uart_source_select) begin //Select CPU1 by default
        UART_BMC_TXD  <= uart_txd[1];
        UART_BMC_RTS  <= uart_rts[1];
        uart_rxd[1]   <= UART_BMC_RXD;
        uart_cts[1]   <= UART_BMC_CTS;        
        uart_rxd[0]   <= 1'b1;
        uart_cts[0]   <= 1'b0; //Don't let UART0 send when UART1 is selected.
    end else begin //UART0 is selected
        UART_BMC_TXD  <= uart_txd[0];
        UART_BMC_RTS  <= uart_rts[0];
        uart_rxd[0]   <= UART_BMC_RXD;
        uart_cts[0]   <= UART_BMC_CTS;
        uart_rxd[1]   <= 1'b1;
        uart_cts[1]   <= 1'b0; //Don't let UART1 send when UART0 is selected.
    end
end

//IOC LVDS Module, Master on SCM side
ioc_top 
    #(
      .MASTER                ( 1                     ),
      .BUS_SPEED_KHZ         ( 400                   ),
      .NORMAL_GPIO_RST_VALUE ( { 24'b0        ,  /*GPIO_RSVD*/
                                 8'b0001_0000 ,  /*GPIO_VALUE_87_80*/
                                 8'b0000_0100 ,  /*GPIO_VALUE_79_72*/
                                 8'b0000_0000 ,  /*GPIO_VALUE_71_64*/
                                 8'b0000_0100 ,  /*GPIO_VALUE_63_56*/
                                 8'b0001_1111 ,  /*GPIO_VALUE_55_48*/
                                 8'b0100_0000 ,  /*GPIO_VALUE_47_40*/
                                 8'b0001_1000 ,  /*GPIO_VALUE_39_32*/
                                 8'b1111_1001 ,  /*GPIO_VALUE_31_24*/
                                 8'b0000_0000 ,  /*GPIO_VALUE_23_16*/
                                 8'b0111_1111 ,  /*GPIO_VALUE_15_8*/
                                 8'b1111_1110    /*GPIO_VALUE_7_0*/	
                             } )
     )
scm_ioc
(
    .clk              ( clk_20m           ),
    .rst_n            ( Reset_N           ),
    .tx_coreclock     ( tx_coreclock      ), //tx_lvds internal pll clock output
    .tx_pll_locked    ( tx_pll_locked     ), //tx_lvds internal pll lock output      
    .aligned          ( mcsi_aligned      ),
//LVDS link    
    .lvds_clk_in      ( LVDS_CLK_RX_DP    ),
    .lvds_clk_out     ( LVDS_CLK_TX_R_DP    ),
    .lvds_rx_in       ( LVDS_RX_DP        ),
    .lvds_tx_out      ( LVDS_TX_R_DP        ),
//SMBus
    .smb_scl          ({ scl_rsv[6:0],
                         SMB_PIROM_LVC3_SCL,
                         SMB_PMBUS1_STBY_LVC3_SCL,
                         SMB_TEMPSENSOR_STBY_LVC3_SCL,   
                         SMB_PMBUS2_STBY_LVC3_SCL,
                         SMB_CHASSIS_SENSOR_STBY_LVC3_SCL   }),
                                                    
    .smb_sda          ({ sda_rsv[6:0],    
                         SMB_PIROM_LVC3_SDA,
                         SMB_PMBUS1_STBY_LVC3_SDA,
                         SMB_TEMPSENSOR_STBY_LVC3_SDA,
                         SMB_PMBUS2_STBY_LVC3_SDA,
                         SMB_CHASSIS_SENSOR_STBY_LVC3_SDA    }),
//gpio_in
    .gpio_in          ( gpio_in                              ),
//gpio_out
    .gpio_out         ({ gpio_out_rsv[20:0], gpio_out[90:0] }),
//UART over LVDS    
    .uart_rxd         ( uart_rxd                             ),     
    .uart_cts         ( uart_cts                             ),      
    .uart_txd         ( uart_txd                             ),
    .uart_rts         ( uart_rts                             ),
//AVMM slave only exist on ioc_master side                   
    .avmm_slv_addr    ( mcsi_address                         ),  
    .avmm_slv_read    ( mcsi_read                            ),  
    .avmm_slv_write   ( mcsi_write                           ),
    .avmm_slv_wdata   ( mcsi_writedata                       ),
    .avmm_slv_byteen  ( mcsi_byteenable                      ),
    .avmm_slv_rdata   ( mcsi_readdata                        ),
    .avmm_slv_rdvalid ( mcsi_readdatavalid                   ),
    .avmm_slv_waitrq  ( mcsi_waitrequest                     ),
//AVMM master only exist on ioc_slave side
    .avmm_mst_addr    (                                      ),  
    .avmm_mst_read    (                                      ),  
    .avmm_mst_write   (                                      ),
    .avmm_mst_wdata   (                                      ),
    .avmm_mst_byteen  (                                      ),
    .avmm_mst_rdata   ( 'b0                                  ),
    .avmm_mst_rdvalid ( 'b0                                  ),
    .avmm_mst_waitrq  ( 'b0                                  ),   
//MCSI_Internal_CSR    
    .avmm_csr_addr    ( mcsi_csr_address[15:0]               ),
    .avmm_csr_read    ( mcsi_csr_read                        ),
    .avmm_csr_write   ( mcsi_csr_write                       ),
    .avmm_csr_wdata   ( mcsi_csr_writedata                   ),
    .avmm_csr_rdata   ( mcsi_csr_readdata                    ),
    .avmm_csr_byteen  ( mcsi_csr_byteenable                  ),
    .avmm_csr_rdvalid ( mcsi_csr_readdatavalid               ),
    .avmm_csr_waitrq  ( mcsi_csr_waitrequest                 ),
//IIC_MM access error report
    .status_reg_mm        ( status_reg_mm                    ),
	 .invalid_access_mcsi  ( invalid_access_scm_mcsi          ),
	 .invalid_access_cpu   ( 'b0                              ),
	 .invalid_access_dbg   ( 'b0                              )
);

avmm_mux_1to4 
  #(
    .SLV1_ADDR_LOW  ( 32'h0000 ),
    .SLV1_ADDR_High ( 32'h00FF ),
    .SLV2_ADDR_LOW  ( 32'h0100 ),
    .SLV2_ADDR_High ( 32'h01FF ),
    .SLV3_ADDR_LOW  ( 32'h0200 ),
    .SLV3_ADDR_High ( 32'h02FF ),
    .SLV4_ADDR_LOW  ( 32'h4000 ),
    .SLV4_ADDR_High ( 32'hFFFF )    
   ) 
avmm_mux_1to4_inst 
(
    .clk                 ( tx_coreclock              ),           
    .rst_n               ( tx_pll_locked             ),
    //AVMM_Single_Master, connected to I2C slave AVMM
    .mst_address         ( avmm_bmc_addr             ),
    .mst_write           ( avmm_bmc_write            ),
    .mst_writedata       ( avmm_bmc_wdata            ),          
    .mst_read            ( avmm_bmc_read             ),          
    .mst_readdata        ( avmm_bmc_rdata            ),      
    .mst_readdatavalid   ( avmm_bmc_rdvalid          ), 
    .mst_waitrequest     ( avmm_bmc_waitrq           ),            
    .mst_byteenable      ( avmm_bmc_byteen           ),      
    .invalid_access      (                           ),	 
    //AVMM_Slave_1, connect to general csr         
    .slv1_address        ( general_csr_address       ),
    .slv1_write          ( general_csr_write         ),
    .slv1_writedata      ( general_csr_writedata     ),          
    .slv1_read           ( general_csr_read          ),          
    .slv1_readdata       ( general_csr_readdata      ),      
    .slv1_readdatavalid  ( general_csr_readdatavalid ), 
    .slv1_waitrequest    ( general_csr_waitrequest   ),            
    .slv1_byteenable     ( general_csr_byteenable    ),
	 .invalid_access_slv1 ( invalid_access_general    ),
    //AVMM_Slave_2, connect to scm global CSR     
    .slv2_address        ( scm_csr_address           ),
    .slv2_write          ( scm_csr_write             ),
    .slv2_writedata      ( scm_csr_writedata         ),          
    .slv2_read           ( scm_csr_read              ),          
    .slv2_readdata       ( scm_csr_readdata          ),      
    .slv2_readdatavalid  ( scm_csr_readdatavalid     ), 
    .slv2_waitrequest    ( scm_csr_waitrequest       ),            
    .slv2_byteenable     ( scm_csr_byteenable        ),
	 .invalid_access_slv2 ( invalid_access_scm_glb    ),
    //AVMM_Slave_3, connect to MCSI CSR
    .slv3_address        ( mcsi_csr_address          ),
    .slv3_write          ( mcsi_csr_write            ),
    .slv3_writedata      ( mcsi_csr_writedata        ),          
    .slv3_read           ( mcsi_csr_read             ),          
    .slv3_readdata       ( mcsi_csr_readdata         ),      
    .slv3_readdatavalid  ( mcsi_csr_readdatavalid    ), 
    .slv3_waitrequest    ( mcsi_csr_waitrequest      ),            
    .slv3_byteenable     ( mcsi_csr_byteenable       ),
	 .invalid_access_slv3 ( invalid_access_scm_mcsi   ),
    //AVMM_Slave_4, connect to MCSI which crosses serial link    
    .slv4_address        ( mcsi_address              ),
    .slv4_write          ( mcsi_write                ),
    .slv4_writedata      ( mcsi_writedata            ),          
    .slv4_read           ( mcsi_read                 ),          
    .slv4_readdata       ( mcsi_readdata             ),      
    .slv4_readdatavalid  ( mcsi_readdatavalid        ), 
    .slv4_waitrequest    ( mcsi_waitrequest          ),            
    .slv4_byteenable     ( mcsi_byteenable           ),
	 .status_reg          ( status_reg                ),
    .status_reg_mm       ( status_reg_mm             )
);

//General CSR store base address and range for each target
general_csr general_csr_inst
(
    .clk                ( tx_coreclock              ),
    .reset              ( !tx_pll_locked            ),
                      
    .avmm_address       ( general_csr_address       ),
    .avmm_write         ( general_csr_write         ),
    .avmm_writedata     ( general_csr_writedata     ),     
    .avmm_read          ( general_csr_read          ),
    .avmm_readdata      ( general_csr_readdata      ),
    .avmm_readdatavalid ( general_csr_readdatavalid ),
    .avmm_waitrequest   ( general_csr_waitrequest   ),        
    .avmm_byteenable    ( general_csr_byteenable    ),
	 //error report
	 .invalid_access     ( invalid_access_general    ),
	 .status_reg         ( status_reg                )
);
//Store global CSR for SCM CPLD
scm_global_csr scm_global_csr_inst
(
    .clk                  ( tx_coreclock              ),
    .reset                ( !tx_pll_locked            ),
    //avmm interface                                
    .avmm_address         ( scm_csr_address           ),
    .avmm_write           ( scm_csr_write             ),
    .avmm_writedata       ( scm_csr_writedata         ),          
    .avmm_read            ( scm_csr_read              ),     
    .avmm_readdata        ( scm_csr_readdata          ),      
    .avmm_readdatavalid   ( scm_csr_readdatavalid     ), 
    .avmm_waitrequest     ( scm_csr_waitrequest       ),           
    .avmm_byteenable      ( scm_csr_byteenable        ),
                                                    
    .mcsi_aligned         ( mcsi_aligned              ),
    .uart_source_sel      ( uart_source_select        ),
    .bmc_force_update_sel ( bmc_force_update_sel      ),
    //error report
    .invalid_access       ( invalid_access_scm_glb    )
);



//Instantiate Platform Logic
dcscm_main
    #(
        .SCM_FPGA_REV      ( 8'h02 ),  // Major Release Version
        .SCM_FPGA_REV_TEST ( 8'h02 )   // Debug Release Version
    )        
dcscm_main_inst
(
    //SCM AUX
    .iClk_2M                    ( clk_2m                     ),
    .iRST_N                     ( Reset_2m_N                 ),
    .PWRGD_P1V05_SCM_AUX        ( PWRGD_P1V05_SCM_AUX        ),     // From P1V05 SCM AUX VR, since this is the last stage SCM card VR, so can indicate all SCM card VRs are fully on
    .PWRGD_P1V0_BMC_AUX         ( PWRGD_P1V0_BMC_AUX         ),     // From P1V0 BMC AUX VR, since this is the last stage runBMC card VR, so can indicate all runBMC card VRs are fully on
    .RST_DEDI_BUSY_CPU0_N       ( RST_DEDI_BUSY_CPU0_N       ),
    .RST_DEDI_BUSY_CPU1_N       ( RST_DEDI_BUSY_CPU1_N       ),
    .iSCM_BMC_EN                ( 1'b1                       ),
    .iCPU1_AUX_PWR_OK           ( wCPU1_AUX_PWR_OK           ),     // From main FPGA through LTPI, indicate CPU1 AUX power rails are fully on
    .BMC_VR_EN                  ( FM_BMC_VR_EN               ),     // To runBMC card first stage VR, enable all runBMC card VRs stage by stage
    //SCM MAIN POWER RAIL                                    
    .PWRGD_P5V_MAIN_SCM         ( PWRGD_P5V_MAIN_SCM         ),     // From SCM P5V main VR, indicate this VR is fully on
    .oP5V_MAIN_PWR_FAULT        ( wP5V_MAIN_PWR_FAULT        ),     // To debug FPGA through LTPI and sGPIO, indicate this VR power failure
    .oFM_P5V_MAIN_SCM_EN        ( FM_P5V_MAIN_SCM_EN         ),     // To SCM P5V main VR, indicate this VR is fully on 
    //PLT LOGIC                                              
    .RST_SRST_BMC_SCM_FPGA_N    ( RST_SRST_BMC_SCM_FPGA_N    ),     // From BMC, indicate BMC SPI flash verified, can start to boot BMC
    .RST_RTCRST_TTK3_N          ( RST_RTCRST_TTK3_N          ),
    .BMC_CMOS_CLEAR_N           ( BMC_CMOS_CLEAR_N           ),     // From BMC, clear CMOS
    .PARTITION_DEBUG_SEL        ( PARTITION_DEBUG_SEL        ),
    .FM_DUAL_PARTITION_R_N      ( FM_DUAL_PARTITION_R_N      ),
    .FM_PARTITION_SEL_R         ( FM_PARTITION_SEL_R         ),
    .iRST_BMC_SRST_DIO_N        ( wRST_BMC_SRST_DIO_N        ),
    .PARTITION_DEBUG_SEL_OUT    ( PARTITION_DEBUG_SEL_OUT    ),
    .FM_VOLTAGE_TRANSLATOR_EN   ( FM_VOLTAGE_TRANSLATOR_EN   ),     // To voltage translater
    .PWRGD_AUX_PWRGD_BMC_CPU0   ( PWRGD_AUX_PWRGD_BMC_CPU0   ),
    //DC-SCM SPEC                                            
    .HPM_STBY_RDY               ( HPM_STBY_RDY               ),     // From main FPGA logic, indicate legacy processor VCCFA_EHV and VNN power rails are fully on
    //PFR related
    .RST_SRST_BMC_PFR_N         ( RST_SRST_BMC_PFR_N         ),     // To PFR, indicate all VRs on SCM card and runBMC card are fully on, can release BMC SRST#
    .cc_PWRGD_AUX_PWRGD_CPU0    ( FM_PWRGD_AUX_PWRGD_CPU0    ),     // To PFR, indicate legacy processor VCCFA_EHV and VNN power rails are fully on, can release CPU_AUX_PWRGD
    .cc_PWRGD_AUX_PWRGD_CPU1    ( FM_PWRGD_AUX_PWRGD_CPU1    ),     // To PFR, indicate CPU1 VCCFA_EHV and VNN power rails are fully on, can release CPU1 AUX_PWRGD
    .PWRGD_AUX_PWRGD_CPU0       ( PWRGD_AUX_PWRGD_CPU0       ),     // From PFR, indicate CPU0 IFWI SPI flash verified
    .PWRGD_AUX_PWRGD_CPU1       ( PWRGD_AUX_PWRGD_CPU1       ),     // From PFR, indicate CPU1 IFWI SPI flash verified
    .RST_PLTRST_CPU0_PFR_LVC3_N ( RST_PLTRST_CPU0_PFR_LVC3_N ),
    .RST_PLTRST_CPU1_PFR_LVC3_N ( RST_PLTRST_CPU1_PFR_LVC3_N ),
    .RST_BMC_RSTBTN_OUT_N       ( RST_BMC_RSTBTN_OUT_N       ),
    .RST_PFR_RTCRST_CPU0_N      ( RST_PFR_RTCRST_CPU0_N      ),
    .RST_PFR_RTCRST_CPU1_N      ( RST_PFR_RTCRST_CPU1_N      ),
    //Signals from CPU FPGA thru LVDS
    .iPWRGD_PS_PWROK_CPU_PLD_R  ( pwrgd_ps_pwrok_sync        ),
    //Signals directly pass thru LVDS to CPU FPGA
    .RST_BMC_PCIE_MUX_N         ( RST_BMC_PCIE_MUX_N         ),
    .RST_BMC_HSBP_MUX_N         ( RST_BMC_HSBP_MUX_N         ),
    .FM_BMC_ONCTL_N             ( FM_BMC_ONCTL_N             ),
    .FP_BMC_PWR_BTN_OUT_N       ( FP_BMC_PWR_BTN_OUT_N       ),
    .FM_BMC_BMCINIT             ( FM_BMC_BMCINIT             ),
    .FP_ID_LED_N                ( FP_ID_LED_N                ),
    .FP_LED_STATUS_AMBER_N      ( FP_LED_STATUS_AMBER_N      ),
    .FP_LED_STATUS_GREEN_N      ( FP_LED_STATUS_GREEN_N      ),
    .SPEAKER_BMC                ( SPEAKER_BMC                ),
    .FM_SKT0_FAULT_LED          ( FM_SKT0_FAULT_LED          ),
    .FM_SKT1_FAULT_LED          ( FM_SKT1_FAULT_LED          ),
    .FM_CPU_FBRK_DEBUG_N        ( FM_CPU_FBRK_DEBUG_N        ),
    .FM_SPD_SWITCH_CTRL_N       ( FM_SPD_SWITCH_CTRL_N       ),
    .FM_TPM_EN_PULSE            ( FM_TPM_EN_PULSE            ),
    .FM_LED_BMC_CPU_RSTIND      ( FM_LED_BMC_CPU_RSTIND      ),
    .A_P3V_BAT_SCALED_EN        ( A_P3V_BAT_SCALED_EN        ),
	 .FM_CK440_REMOTESSC_GPIO0   ( FM_CK440_REMOTESSC_GPIO0   ),
	 .FM_CK440_REMOTESSC_GPIO1   ( FM_CK440_REMOTESSC_GPIO1   ),
	 .FM_BMC_TRUST_N             ( FM_BMC_TRUST_N             ),
    //SCM To CPU CPLD
    .oRST_BMC_PCIE_MUX_N        ( wRST_BMC_PCIE_MUX_N        ),
    .oRST_BMC_HSBP_MUX_N        ( wRST_BMC_HSBP_MUX_N        ),
    .oFM_BMC_ONCTL_N            ( wFM_BMC_ONCTL_N            ),
    .oFP_BMC_PWR_BTN_OUT_N      ( wFP_BMC_PWR_BTN_OUT_N      ),
    .oFM_BMC_BMCINIT            ( wFM_BMC_BMCINIT            ),
    .oFP_ID_LED_N               ( wFP_ID_LED_N               ),
    .oFP_LED_STATUS_AMBER_N     ( wFP_LED_STATUS_AMBER_N     ),
    .oFP_LED_STATUS_GREEN_N     ( wFP_LED_STATUS_GREEN_N     ),
    .oSPEAKER_BMC               ( wSPEAKER_BMC               ),
    .oFM_SKT0_FAULT_LED         ( wFM_SKT0_FAULT_LED         ),
    .oFM_SKT1_FAULT_LED         ( wFM_SKT1_FAULT_LED         ),
    .oFM_CPU_FBRK_DEBUG_N       ( wFM_CPU_FBRK_DEBUG_N       ),
    .oFM_SPD_SWITCH_CTRL_N      ( wFM_SPD_SWITCH_CTRL_N      ),
    .oFM_TPM_EN_PULSE           ( wFM_TPM_EN_PULSE           ),
    .oFM_LED_BMC_CPU_RSTIND     ( wFM_LED_BMC_CPU_RSTIND     ),
    .oA_P3V_BAT_SCALED_EN       ( wA_P3V_BAT_SCALED_EN       ),
    .oRST_BMC_RSTBTN_OUT_N      ( wRST_BMC_RSTBTN_OUT_N      ),
    .oFM_CK440_REMOTESSC_GPIO0  ( wFM_CK440_REMOTESSC_GPIO0  ),
	 .oFM_CK440_REMOTESSC_GPIO1  ( wFM_CK440_REMOTESSC_GPIO1  ),    
    //Signals be used  both inside dcscm_main.v module and pss thru to LVDS 
    .oRST_RTC_RST_CPU0          ( wRST_RTC_RST_CPU0          ),//Internal logic generate, tunnel to LVDS
    .oRST_RTC_RST_CPU1          ( wRST_RTC_RST_CPU1          ),//Internal logic generate, tunnel to LVDS
    .oSCM_BMC_AUX_PWR_OK        ( HPM_STBY_EN                ),//Indicate DC-SCM module powers on, send out enable signal to enable legacy processor AUX power rail
    .oSCM_BMC_AUX_PWR_FAULT     ( wSCM_BMC_AUX_PWR_FAULT     ),//Internal logic generate, tunnel to LVDS
    .oSCM_PWR_FAULT             ( wSCM_PWR_FAULT             ),//Internal logic generate, tunnel to LVDS
    .oBMC_PWR_FAULT             ( wBMC_PWR_FAULT             ),//Internal logic generate, tunnel to LVDS
    .oRST_PLTRST_CPU0_PFR_LVC3_N( wRST_PLTRST_CPU0_PFR_LVC3_N),     // To main FPGA through LTPI
    .oRST_PLTRST_CPU1_PFR_LVC3_N( wRST_PLTRST_CPU1_PFR_LVC3_N),     // To main FPGA through LTPI
    .oPWRGD_AUX_PWRGD_CPU0      ( wPWRGD_AUX_PWRGD_CPU0      ),     // To main FPGA through LTPI
    .oPWRGD_AUX_PWRGD_CPU1      ( wPWRGD_AUX_PWRGD_CPU1      ),     // To main FPGA through LTPI
    .oFM_DUAL_PARTITION_R_N     ( wFM_DUAL_PARTITION_R_N     ),//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
    .oFM_PARTITION_SEL_R        ( wFM_PARTITION_SEL_R        ),//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
    .oSCMFPGAREV                ( wSCMFPGAREV                ),
    .oSCMFPGATEST               ( wSCMFPGATEST               )
);

assign wLED_CPU0_DIMM_CH1_8_FLT = {wLED_CPU0_CHA_DIMM1_FAULT,wLED_CPU0_CHB_DIMM1_FAULT,wLED_CPU0_CHC_DIMM1_FAULT,wLED_CPU0_CHD_DIMM1_FAULT,wLED_CPU0_CHE_DIMM1_FAULT,wLED_CPU0_CHF_DIMM1_FAULT,wLED_CPU0_CHG_DIMM1_FAULT,wLED_CPU0_CHH_DIMM1_FAULT};
assign wLED_CPU1_DIMM_CH1_8_FLT = {wLED_CPU1_CHA_DIMM1_FAULT,wLED_CPU1_CHB_DIMM1_FAULT,wLED_CPU1_CHC_DIMM1_FAULT,wLED_CPU1_CHD_DIMM1_FAULT,wLED_CPU1_CHE_DIMM1_FAULT,wLED_CPU1_CHF_DIMM1_FAULT,wLED_CPU1_CHG_DIMM1_FAULT,wLED_CPU1_CHH_DIMM1_FAULT};

assign wLED_CPU0_DIMM_CH9_12_FLT = {wLED_CPU0_CHI_DIMM1_FAULT,wLED_CPU0_CHJ_DIMM1_FAULT,wLED_CPU0_CHK_DIMM1_FAULT,wLED_CPU0_CHL_DIMM1_FAULT};

assign wLED_CPU1_DIMM_CH9_12_FLT = {wLED_CPU1_CHI_DIMM1_FAULT,wLED_CPU1_CHJ_DIMM1_FAULT,wLED_CPU1_CHK_DIMM1_FAULT,wLED_CPU1_CHL_DIMM1_FAULT};


//Binding GPIO through LVDS
//GPIO_IN
assign gpio_in = {
                    18'b0,
						  wSCMFPGAREV,                    //8 bits signal
						  wSCMFPGATEST,                   //8 bits signal
						  //GPIO in 79:72
						  FM_TTK_SPI_EN_RJC_N_IN, // sGPIO 77
						  PFR_DEBUG_JUMPER_RJC_N_IN,
						  PFR_FORCE_RECOVERY_RJC_N_IN,
						  wFM_BMC_INIT_DONE,
						  wFM_GLOBAL_RESET,
						  wFM_CPU1_INTR_CLK_CONFDONE,
						  //GPIO in 71:64
                    wLED_CPU0_DIMM_CH1_8_FLT,      //8 bits signal
                    //GPIO in 63:56
                    wLED_CPU1_DIMM_CH1_8_FLT,      //8 bits signal
                    //GPIO in 55:48
						  wLED_CPU0_DIMM_CH9_12_FLT,      //4 bits signal
                    wLED_CPU1_DIMM_CH9_12_FLT,      //4 bits signal
						  //GPIO in 47:40
						  wSURPRISE_RESET,
						  FM_BMC_TRUST_N,
						  wRST_BMC_RSTBTN_OUT_N,
						  wRST_RTC_RST_CPU1,
                    wRST_BMC_PCIE_MUX_N,    
                    wRST_BMC_HSBP_MUX_N,    
                    wFM_BMC_ONCTL_N,
                    wFP_BMC_PWR_BTN_OUT_N,  
						  //GPIO in 39:32
                    wFM_BMC_BMCINIT,        
                    wFP_ID_LED_N,           
                    wFP_LED_STATUS_AMBER_N, 
                    wFP_LED_STATUS_GREEN_N, 
                    wSPEAKER_BMC,           
                    wFM_SKT0_FAULT_LED,     
                    wFM_SKT1_FAULT_LED,     
                    wFM_CPU_FBRK_DEBUG_N,
						  //GPIO in 31:24
                    wFM_SPD_SWITCH_CTRL_N,  
                    wFM_TPM_EN_PULSE,      
                    wFM_LED_BMC_CPU_RSTIND, 
                    wA_P3V_BAT_SCALED_EN,
                    wRST_RTC_RST_CPU0,                  
                    1'b0,        
                    wSCM_BMC_AUX_PWR_FAULT,     
                    wSCM_PWR_FAULT,
                    //GPIO in 23:16						  
                    wBMC_PWR_FAULT,
                    wP5V_MAIN_PWR_FAULT,             
                    wRST_PLTRST_CPU0_PFR_LVC3_N,
                    wRST_PLTRST_CPU1_PFR_LVC3_N,
                    wPWRGD_AUX_PWRGD_CPU0,      
                    wPWRGD_AUX_PWRGD_CPU1,      
                    wFM_CK440_REMOTESSC_GPIO0,     
                    wFM_CK440_REMOTESSC_GPIO1,
                    //GPIO in 15:8						  
                    wBIOS_POST_CODE_LED_0,
                    wBIOS_POST_CODE_LED_1,
                    wBIOS_POST_CODE_LED_2,
                    wBIOS_POST_CODE_LED_3,
                    wBIOS_POST_CODE_LED_4,
                    wBIOS_POST_CODE_LED_5, 
                    wBIOS_POST_CODE_LED_6,
                    wBIOS_POST_CODE_LED_7,
						  //GPIO in 7:0
                    wPFR_POST_CODE_LED_0,
                    wPFR_POST_CODE_LED_1,
                    wPFR_POST_CODE_LED_2,
                    wPFR_POST_CODE_LED_3,
                    wPFR_POST_CODE_LED_4,
                    wPFR_POST_CODE_LED_5,
                    wPFR_POST_CODE_LED_6,
                    wPFR_POST_CODE_LED_7   
                   };

//GPIO_OUT						 
assign wPWRGD_S0_PWROK_CPU0           =  gpio_out[90] ;    //default value 1'b0,   To BMC thru sGPIO to support ASD
assign FM_TTK_SPI_EN_RJC_N_Override        =   gpio_out[89];    //default value 1'b0,  output to RJC pin;
assign PFR_DEBUG_JUMPER_RJC_N_Override     =   gpio_out[88];    //default value 1'b0,  output to RJC pin;
//GPIO out 87:80
assign PFR_FORCE_RECOVERY_RJC_N_Override   =   gpio_out[87];	   //default value 1'b1,  output to RJC pin;
assign FM_TTK_SPI_EN_RJC_N_Value        =   gpio_out[86];    //default value 1'b0,  output to RJC pin;
assign PFR_DEBUG_JUMPER_RJC_N_Value     =   gpio_out[85];    //default value 1'b0,  output to RJC pin;
assign PFR_FORCE_RECOVERY_RJC_N_Value   =   gpio_out[84];	   //default value 1'b1,  output to RJC pin;
assign wCPU_MISMATCH                  =  gpio_out[83] ;    //default value 1'b0,   Directly out to board              
assign wMEM_PWR_FLT                   =  gpio_out[82] ;    //default value 1'b0,   Directly out to board
assign wCPU_PWR_FLT                   =  gpio_out[81] ;    //default value 1'b0,   Directly out to board                
assign wPSU_PWR_FLT                   =  gpio_out[80] ;    //default value 1'b0,   Directly out to board
//GPIO out 79:72
assign wP3V3_FAULT                    =  gpio_out[79] ;    //default value 1'b0,   Directly out to board
assign wCPU_AUX_PWR_FLT               =  gpio_out[78] ;    //default value 1'b0,   Directly out to board
assign FM_DUAL_PARTITION_R_N          =  gpio_out[77] ;    //default value 1'b0,   Directly out to board
assign FM_PARTITION_SEL_R             =  gpio_out[76] ;    //default value 1'b0,   Directly out to board
assign wFM_VAL_DBG_JUMPER_EN          =  gpio_out[75] ;    //default value 1'b0,   To BMC thru sGPIO
assign FM_BIOS_IMAGE_SWAP_N           =  gpio_out[74] ;    //default value 1'b1,   Directly out to board						 
assign wFM_BOARD_SKU_ID5              =  gpio_out[73] ;    //default value 1'b0,   To BMC thru sGPIO						 
assign RST_PLTRST_CPU0_LVC3_N         =  gpio_out[72] ;    //default value 1'b0,   Directly out to PFR
//GPIO out 71:64
assign RST_PLTRST_CPU1_LVC3_N         =  gpio_out[71] ;    //default value 1'b0,   Directly out to PFR						 
assign FM_BMC_SAFS_SEL                =  gpio_out[70] ;    //default value 1'b0,   Directly out to board						 
assign PWRGD_PS_PWROK_SCM_PLD_R       =  gpio_out[69] ;    //default value 1'b0,   Signal out to board and used by internal module
assign FM_SLPS4_N                     =  gpio_out[68] ;    //default value 1'b0,   Directly out to board, this is CPU0 SLPS4 signal to BMC  
assign FM_SLPS3_N                     =  gpio_out[67] ;    //default value 1'b0,   Directly out to board, this is CPU0 SLPS3 signal to BMC  
assign wPWRGD_CPU0_LVC3               =  gpio_out[66] ;    //default value 1'b0,   Directly out to board  
assign wFM_SLPS4_CPU1_CPU_PLD_N       =  gpio_out[65] ;    //default value 1'b0;
assign wFM_SLPS3_CPU1_CPU_PLD_N       =  gpio_out[64] ;    //default value 1'b0;
//GPIO out 63:56  
assign wFM_CPU0_PKGID0                =  gpio_out[63] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU0_PKGID1                =  gpio_out[62] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU0_PKGID2                =  gpio_out[61] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU0_PROC_ID0              =  gpio_out[60] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU0_PROC_ID1              =  gpio_out[59] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU0_SKTOCC_LVT3_PLD_N     =  gpio_out[58] ;    //default value 1'b1,   To BMC thru sGPIO  
assign wFM_CPU1_PKGID0                =  gpio_out[57] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU1_PKGID1                =  gpio_out[56] ;    //default value 1'b0,   To BMC thru sGPIO
//GPIO out 55:48  
assign wFM_CPU1_PKGID2                =  gpio_out[55] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU1_PROC_ID0              =  gpio_out[54] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU1_PROC_ID1              =  gpio_out[53] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_CPU1_SKTOCC_LVT3_PLD_N     =  gpio_out[52] ;    //default value 1'b1,   To BMC thru sGPIO  
assign FP_BMC_PWR_BTN_N               =  gpio_out[51] ;    //default value 1'b1,   Directly out to board  
assign FP_RST_BTN_N                   =  gpio_out[50] ;    //default value 1'b1,   Directly out to board  
assign FP_ID_BTN_N                    =  gpio_out[49] ;    //default value 1'b1,   Directly out to board  
assign FP_NMI_BTN_N                   =  gpio_out[48] ;    //default value 1'b1,   Directly out to board
//GPIO out 47:40  
assign wFM_SERIAL_BOOT                =  gpio_out[47] ;    //default value 1'b1,   To BMC thru sGPIO  
assign NVME_LVC3_ALERT_N              =  gpio_out[46] ;    //default value 1'b1,   Directly out to board  
assign wRST_BMC_SRST_DIO_N            =  gpio_out[45] ;    //default value 1'b0;  
assign wFM_BOARD_SKU_ID0              =  gpio_out[44] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_BOARD_SKU_ID1              =  gpio_out[43] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_BOARD_SKU_ID2              =  gpio_out[42] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_BOARD_SKU_ID3              =  gpio_out[41] ;    //default value 1'b0,   To BMC thru sGPIO  
assign wFM_BOARD_SKU_ID4              =  gpio_out[40] ;    //default value 1'b0,   To BMC thru sGPIO
//GPIO out 39:32  
assign wFM_BOARD_REV_ID0              =  gpio_out[39] ;    //default value 1'b0,   To BMC thru sGPIO
assign wFM_BOARD_REV_ID1              =  gpio_out[38] ;    //default value 1'b0,   To BMC thru sGPIO
assign wFM_BOARD_REV_ID2              =  gpio_out[37] ;    //default value 1'b0,   To BMC thru sGPIO
assign FM_STANDALONE_MODE_N           =  gpio_out[36] ;    //default value 1'b1,   Directly out to board
assign FM_4S_8S_MODE_N                =  gpio_out[35] ;    //default value 1'b1,   Directly out to board
assign FM_NODE_ID0                    =  gpio_out[34] ;    //default value 1'b0,   Directly out to board
assign FM_NODE_ID1                    =  gpio_out[33] ;    //default value 1'b0,   Directly out to board
assign wFM_1200VA_OC                  =  gpio_out[32] ;    //default value 1'b0,   Directly out to board
//GPIO out 31:24
assign IRQ_PMBUS_ALERT_N              =  gpio_out[31] ;    //default value 1'b1,   Directly out to board                                                    
assign wIRQ_CPU0_VRHOT_N              =  gpio_out[30] ;    //default value 1'b1,   To BMC thru sGPIO
assign wIRQ_CPU1_VRHOT_N              =  gpio_out[29] ;    //default value 1'b1,   To BMC thru sGPIO
assign wIRQ_CPU0_MEM_VRHOT_N          =  gpio_out[28] ;    //default value 1'b1,   To BMC thru sGPIO
assign wIRQ_CPU1_MEM_VRHOT_N          =  gpio_out[27] ;    //default value 1'b1,   To BMC thru sGPIO
assign wFM_S3M_CPU0_CPLD_CRC_ERROR    =  gpio_out[26] ;    //default value 1'b0,   To BMC thru sGPIO
assign wFM_S3M_CPU1_CPLD_CRC_ERROR    =  gpio_out[25] ;    //default value 1'b0,   To BMC thru sGPIO
assign DBG_GPIO_POD_PRSNT_N           =  gpio_out[24] ;    //default value 1'b1,   Directly out to board
//GPIO out 23:16
assign wH_CPU0_CATERR_LVC1_ENCODE[0]  =  gpio_out[23] ;    //default value 1'b0,   To BMC thru sGPIO
assign wH_CPU0_CATERR_LVC1_ENCODE[1]  =  gpio_out[22] ;    //default value 1'b0,   To BMC thru sGPIO
assign wH_CPU0_RMCA_LVC1_ENCODE[0]    =  gpio_out[21] ;    //default value 1'b0,   To BMC thru sGPIO
assign wH_CPU0_RMCA_LVC1_ENCODE[1]    =  gpio_out[20] ;    //default value 1'b0,   To BMC thru sGPIO
assign wH_CPU1_CATERR_LVC1_ENCODE[0]  =  gpio_out[19] ;    //default value 1'b0,   To BMC thru sGPIO
assign wH_CPU1_CATERR_LVC1_ENCODE[1]  =  gpio_out[18] ;    //default value 1'b0,   To BMC thru sGPIO
assign wH_CPU1_RMCA_LVC1_ENCODE[0]    =  gpio_out[17] ;    //default value 1'b0,   To BMC thru sGPIO
assign wH_CPU1_RMCA_LVC1_ENCODE[1]    =  gpio_out[16] ;    //default value 1'b0,   To BMC thru sGPIO
//GPIO out 15:8
assign DBG_GPIO_JUMPER_EN_DET         =  gpio_out[15] ;    //default value 1'b0,   Directly out to board
assign wH_CPU0_THERMTRIP_LVC1_N       =  gpio_out[14] ;    //default value 1'b1,   To BMC thru sGPIO
assign wH_CPU0_MEMTRIP_LVC1_N         =  gpio_out[13] ;    //default value 1'b1,   To BMC thru sGPIO
assign wH_CPU0_MEMHOT_OUT_LVC1_N      =  gpio_out[12] ;    //default value 1'b1,   To BMC thru sGPIO
assign wH_CPU0_ERR0_LVC1_N            =  gpio_out[11] ;    //default value 1'b1,   Directly out to board
assign wH_CPU0_ERR1_LVC1_N            =  gpio_out[10] ;    //default value 1'b1,   Directly out to board
assign wH_CPU0_ERR2_LVC1_N            =  gpio_out[9]  ;    //default value 1'b1,   Directly out to board
assign wH_CPU0_MON_FAIL_PLD_LVC1_N    =  gpio_out[8]  ;    //default value 1'b1,   To BMC thru sGPIO
//GPIO out 7:0
assign wH_CPU1_THERMTRIP_LVC1_N       =  gpio_out[7]  ;    //default value 1'b1,   To BMC thru sGPIO
assign wH_CPU1_MEMTRIP_LVC1_N         =  gpio_out[6]  ;    //default value 1'b1,   To BMC thru sGPIO
assign wH_CPU1_MEMHOT_OUT_LVC1_N      =  gpio_out[5]  ;    //default value 1'b1,   To BMC thru sGPIO
assign wH_CPU1_ERR0_LVT1_N            =  gpio_out[4]  ;    //default value 1'b1,   Directly out to board
assign wH_CPU1_ERR1_LVT1_N            =  gpio_out[3]  ;    //default value 1'b1,   Directly out to board
assign wH_CPU1_ERR2_LVT1_N            =  gpio_out[2]  ;    //default value 1'b1,   Directly out to board
assign wH_CPU1_MON_FAIL_PLD_LVC1_N    =  gpio_out[1]  ;    //default value 1'b1,   To BMC thru sGPIO 
assign wCPU1_AUX_PWR_OK               =  gpio_out[0]  ;    // To SCM FPGA logic, indicate CPU1 AUX power rails are fully on


//sGPIO instance
ngsx #(
        .IN_BYTE_REGS (16),
        .OUT_BYTE_REGS (16),
        //RESET VALUE FOR DATA COME FROM BMC
        .RST_VALUE_IN(128'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
        //RESET VALUE FOR DATA GO TO BMC
        .RST_VALUE_OUT(128'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0100_0000_0000_0000_0000_1000_1000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_1111_1100_0011_1111)
      
     ) bmc_sgpio
    (
        .iRst_n(Reset_sGPIO_BMC_N),     // active low reset signal (driven from internal FPGA logic)
        .iClk  (SGPIO_BMC_CLK),         // serial clock (driven from SGPIO master)
        .iLoad (SGPIO_BMC_LD_N),        // Load signal (driven from SGPIO master to capture serial data input in parallel register)
        .iSData(SGPIO_BMC_DOUT),        // Serial data input (driven from SGPIO master)
        .iPData({                       // SCM FPGA to BMC
                                        // Below is byte0 (sGPIO[7:0]), default value 8'b0011_1111											 
                                        wFM_CPU0_PROC_ID1,               // DIN 7, indicates processor ID1 of CPU mounted on SKT0
                                        wFM_CPU0_PROC_ID0,               // DIN 6, indicates processor ID0 of CPU mounted on SKT0
                                        wH_CPU0_MEMHOT_OUT_LVC1_N,       // DIN 5, indicates one of the DIMMs on CPU0 has reach a thermal limitation
                                        wIRQ_CPU0_MEM_VRHOT_N,           // DIN 4, indicates CPU0 memory VR controller (Channels 0, 1 and 2) VR_HOT_N events
                                        wH_CPU0_MON_FAIL_PLD_LVC1_N,     // DIN 3, indicates CPU0 internal hardware errors
                                        wIRQ_CPU0_VRHOT_N,               // DIN 2, indicates CPU0 VCCIN/PVCCFA_EHV_FIVRA/PVCCFA_EHV/PVCCINFAON VR_HOT_N events
                                        wH_CPU0_THERMTRIP_LVC1_N,        // DIN 1, indicates CPU0_THERMTRIP_N events
                                        wFM_CPU0_SKTOCC_LVT3_PLD_N,      // DIN 0, indicates if CPU0 is populated
 
                                        // Below is byte1 (sGPIO[15:8]), default value 8'b1111_1100
                                        wH_CPU1_MEMHOT_OUT_LVC1_N,       // DIN15, indicates one of the DIMMs on CPU1 has reach a thermal limitation
                                        wIRQ_CPU1_MEM_VRHOT_N,           // DIN14, indicates CPU1 memory VR controller (Channels 0, 1 and 2) VR_HOT_N events
                                        wH_CPU1_MON_FAIL_PLD_LVC1_N,     // DIN13, indicates CPU1 internal hardware errors
                                        wIRQ_CPU1_VRHOT_N,               // DIN12, indicates CPU1 VCCIN/PVCCFA_EHV_FIVRA/PVCCFA_EHV/PVCCINFAON VR_HOT_N events
                                        wH_CPU1_THERMTRIP_LVC1_N,        // DIN11, indicates CPU1_THERMTRIP_N events
                                        wFM_CPU1_SKTOCC_LVT3_PLD_N,      // DIN10, indicates if CPU1 is populated
                                        1'b0,                            // DIN 9, SPARE
                                        wCPU_MISMATCH,                   // DIN 8, indicates mistmaches of CPU mounted on SKT0 related to CPU's PKGID pins

                                        // Below is byte2 (sGPIO[23:16]), default value 8'b0000_0000	
                                        5'b0,                            // DIN23-19, SPARE
                                        wCPU_MISMATCH,                   // DIN18, indicates mistmaches of CPU mounted on SKT1 related to CPU's PKGID pins
                                        wFM_CPU1_PROC_ID1,               // DIN17, indicates processor ID0 of CPU mounted on SKT0
                                        wFM_CPU1_PROC_ID0,               // DIN16, indicates processor ID0 of CPU mounted on SKT0

                                        // Below is byte3 (sGPIO[31:24]), default value 8'b0000_0000	
                                        8'b0,                            // DIN31-24, SPARE

                                        // Below is byte4 (sGPIO[39:32]), default value 8'b0000_0000											
                                        wFM_S3M_CPU0_CPLD_CRC_ERROR,     // DIN39, indicates CPU0 CRC error
                                        7'b0,                            // DIN38-32, SPARE
	 
                                        // Below is byte5 (sGPIO[47:40]), default value 8'b0000_0000
                                        3'b0,                            // DIN47-45, SPARE
                                        wH_CPU1_CATERR_LVC1_ENCODE[0],   // DIN44, indicates CPU1 machine check catastrophic error
                                        wH_CPU1_CATERR_LVC1_ENCODE[1],   // DIN43, indicates CPU1 uncorrectable catastrophic error
                                        wH_CPU0_CATERR_LVC1_ENCODE[0],   // DIN42, indicates CPU0 machine check catastrophic error
                                        wH_CPU0_CATERR_LVC1_ENCODE[1],   // DIN41, indicates CPU0 uncorrectable catastrophic error
                                        wFM_S3M_CPU1_CPLD_CRC_ERROR,     // DIN40, indicates CPU1 CRC error

                                        // Below is byte6 (sGPIO[55:48]), default value 8'b0000_0000	
                                        8'b0,                            // DIN55-48, SPARE

                                        // Below is byte7 (sGPIO[63:56]), default value 8'b0000_0000
                                        wCPU_AUX_PWR_FLT,                // DIN63, indicates a power fault on legacy CPU AUX power domain
                                        2'b0,                            // DIN62-61, SPARE 
                                        wPSU_PWR_FLT,                    // DIN60, indicates a power fault on PSU
                                        wP3V3_FAULT,                     // DIN59, indicates a power fault on P3V3 VR
                                        wCPU_PWR_FLT,                    // DIN58, indicates a power fault on CPU0 or CPU1
                                        wMEM_PWR_FLT,                    // DIN57, indicates a power fault on DIMM
                                        1'b0,                            // DIN56, FM_PVCC_GT_CFP, indicates catastrophic failure events from VCC core/GT VR
 
                                        // Below is byte8 (sGPIO[71:64]), default value 8'b1000_1000
                                        wH_CPU1_MEMTRIP_LVC1_N,          // DIN71, indicates CPU1_MEMMTRIP_N events
                                        wFM_CPU1_PKGID2,                 // DIN70, indicates package ID2 of CPU mounted on SKT1
                                        wFM_CPU1_PKGID1,                 // DIN69, indicates package ID1 of CPU mounted on SKT1
                                        wFM_CPU1_PKGID0,                 // DIN68, indicates package ID0 of CPU mounted on SKT1
                                        wH_CPU0_MEMTRIP_LVC1_N,          // DIN67, indicates CPU0_MEMTRIP_N events
                                        wFM_CPU0_PKGID2,                 // DIN66, indicates package ID2 of CPU mounted on SKT0
                                        wFM_CPU0_PKGID1,                 // DIN65, indicates package ID1 of CPU mounted on SKT0
                                        wFM_CPU0_PKGID0,                 // DIN64, indicates package ID0 of CPU mounted on SKT0
	 
                                        // Below is byte9 (sGPIO[79:72]), default value 8'b0000_0000											
                                        8'b0,                            // DIN79-72, SPARE

                                        // Below is byte10 (sGPIO[87:80]), default value 8'b0000_0000
                                        wFM_BOARD_SKU_ID4,               // DIN87, indicates board SKU ID4
                                        wFM_BOARD_SKU_ID3,               // DIN86, indicates board SKU ID3
                                        wFM_BOARD_SKU_ID2,               // DIN85, indicates board SKU ID2
                                        wFM_BOARD_SKU_ID1,               // DIN84, indicates board SKU ID1
                                        wFM_BOARD_SKU_ID0,               // DIN83, indicates board SKU ID0
                                        wFM_BOARD_REV_ID2,               // DIN82, indicates board revision ID2
                                        wFM_BOARD_REV_ID1,               // DIN81, indicates board revision ID1
                                        wFM_BOARD_REV_ID0,               // DIN80, indicates board revision ID0

                                        // Below is byte11 (sGPIO[95:88]), default value 8'b0000_0100            
                                        3'b0,                            // DIN95-93, SPARE
                                        wPWRGD_S0_PWROK_CPU0,            // DIN92, indicates S0 power rails have been established
                                        1'b0,                            // DIN91, FM_RICH1S_PRESENT, indicates rich one socket SKU
                                        wFM_SERIAL_BOOT,                 // DIN90, indicates parallel/serial boot
                                        wFM_VAL_DBG_JUMPER_EN,           // DIN89, indicates validation jumpers enabled
                                        wFM_BOARD_SKU_ID5,               // DIN88, indicates board SKU ID5

                                        // Below is byte9 (sGPIO[103:96]), default value 8'b0000_0000											
                                        4'b0,                            // DIN103-100, SPARE
                                        wFM_1200VA_OC,                   // DIN99, indicates 1440VA_OC status
                                        3'b0,                            // DIN98-96, SPARE
                                        
                                        // Below is reserved (sGPIO[127:96]), default value 24'b0
                                        24'b0                            // DIN127-96, SPARE
                 }),

     
        .oSData(SGPIO_BMC_DIN_R),       // Serial data output to SGPIO master

        .oPData({                       // BMC to SCM FPGA
                                        // Below is byte12 (sGPIO[99:96]), default value 4'b0000
                                        wFM_BMC_INIT_DONE,               // DOUT99, indicates BMC fully boot down, then system will power up legacy CPU AUX power rails
                                        wFM_GLOBAL_RESET,                // DOUT98, triggers global reset at the end of crash log flow
                                        wFM_CPU1_INTR_CLK_CONFDONE,      // DOUT97, indicates CPU1 intr configuration is completed
                                        wSURPRISE_RESET,                 // DOUT96, triggers warm reset after system hang at boot stage

                                        // Below is byte11 (sGPIO[95:88]), default value 8'b0000_0000
                                        wLED_CPU1_CHL_DIMM2_FAULT,       // DOUT95, controls socket 1 channel L DIMM1 fault LED signal
                                        wLED_CPU1_CHL_DIMM1_FAULT,       // DOUT94, controls socket 1 channel L DIMM0 fault LED signal
                                        wLED_CPU1_CHK_DIMM2_FAULT,       // DOUT93, controls socket 1 channel K DIMM1 fault LED signal
                                        wLED_CPU1_CHK_DIMM1_FAULT,       // DOUT92, controls socket 1 channel K DIMM0 fault LED signal
                                        wLED_CPU1_CHJ_DIMM2_FAULT,       // DOUT91, controls socket 1 channel J DIMM1 fault LED signal
                                        wLED_CPU1_CHJ_DIMM1_FAULT,       // DOUT90, controls socket 1 channel J DIMM0 fault LED signal
                                        wLED_CPU1_CHI_DIMM2_FAULT,       // DOUT89, controls socket 1 channel I DIMM1 fault LED signal
                                        wLED_CPU1_CHI_DIMM1_FAULT,       // DOUT88, controls socket 1 channel I DIMM0 fault LED signal

                                        // Below is byte10 (sGPIO[87:80]), default value 8'b0000_0000
                                        wLED_CPU0_CHL_DIMM2_FAULT,       // DOUT87, controls socket 0 channel L DIMM1 fault LED signal
                                        wLED_CPU0_CHL_DIMM1_FAULT,       // DOUT86, controls socket 0 channel L DIMM0 fault LED signal
                                        wLED_CPU0_CHK_DIMM2_FAULT,       // DOUT85, controls socket 0 channel K DIMM1 fault LED signal
                                        wLED_CPU0_CHK_DIMM1_FAULT,       // DOUT84, controls socket 0 channel K DIMM0 fault LED signal
                                        wLED_CPU0_CHJ_DIMM2_FAULT,       // DOUT83, controls socket 0 channel J DIMM1 fault LED signal
                                        wLED_CPU0_CHJ_DIMM1_FAULT,       // DOUT82, controls socket 0 channel J DIMM0 fault LED signal
                                        wLED_CPU0_CHI_DIMM2_FAULT,       // DOUT81, controls socket 0 channel I DIMM1 fault LED signal
                                        wLED_CPU0_CHI_DIMM1_FAULT,       // DOUT80, controls socket 0 channel I DIMM0 fault LED signal

                                        // Below is byte9 (sGPIO[79:72]), default value 8'b0000_0000
                                        wReserved_3,

                                        // Below is byte8 (sGPIO[71:64]), default value 8'b0000_0000
                                        wLED_CPU1_CHH_DIMM2_FAULT,       // DOUT71, controls socket 1 channel H DIMM1 fault LED signal
                                        wLED_CPU1_CHH_DIMM1_FAULT,       // DOUT70, controls socket 1 channel H DIMM0 fault LED signal
                                        wLED_CPU1_CHG_DIMM2_FAULT,       // DOUT69, controls socket 1 channel G DIMM1 fault LED signal
                                        wLED_CPU1_CHG_DIMM1_FAULT,       // DOUT68, controls socket 1 channel G DIMM0 fault LED signal
                                        wLED_CPU0_CHH_DIMM2_FAULT,       // DOUT67, controls socket 0 channel H DIMM1 fault LED signal
                                        wLED_CPU0_CHH_DIMM1_FAULT,       // DOUT66, controls socket 0 channel H DIMM0 fault LED signal
                                        wLED_CPU0_CHG_DIMM2_FAULT,       // DOUT65, controls socket 0 channel G DIMM1 fault LED signal
                                        wLED_CPU0_CHG_DIMM1_FAULT,       // DOUT64, controls socket 0 channel G DIMM0 fault LED signal

                                        // Below is byte5-7 (sGPIO[63:40]), default value 32'b0
                                        wReserved_2,                     // DOUT63-40, SPARE

                                        // Below is byte4 (sGPIO[39:32]), default value 8'b0000_0000
                                        wLED_CPU1_CHF_DIMM2_FAULT,       // DOUT39, controls socket 1 channel F DIMM1 fault LED signal
                                        wLED_CPU1_CHF_DIMM1_FAULT,       // DOUT38, controls socket 1 channel F DIMM0 fault LED signal
                                        wLED_CPU1_CHE_DIMM2_FAULT,       // DOUT37, controls socket 1 channel E DIMM1 fault LED signal
                                        wLED_CPU1_CHE_DIMM1_FAULT,       // DOUT36, controls socket 1 channel E DIMM0 fault LED signal
                                        wLED_CPU1_CHD_DIMM2_FAULT,       // DOUT35, controls socket 1 channel D DIMM1 fault LED signal
                                        wLED_CPU1_CHD_DIMM1_FAULT,       // DOUT34, controls socket 1 channel D DIMM0 fault LED signal
                                        wLED_CPU1_CHC_DIMM2_FAULT,       // DOUT33, controls socket 1 channel C DIMM1 fault LED signal
                                        wLED_CPU1_CHC_DIMM1_FAULT,       // DOUT32, controls socket 1 channel C DIMM0 fault LED signal

                                        // Below is byte3 (sGPIO[31:24]), default value 8'b0000_0000
                                        wLED_CPU1_CHB_DIMM2_FAULT,       // DOUT31, controls socket 1 channel B DIMM1 fault LED signal
                                        wLED_CPU1_CHB_DIMM1_FAULT,       // DOUT30, controls socket 1 channel B DIMM0 fault LED signal
                                        wLED_CPU1_CHA_DIMM2_FAULT,       // DOUT29, controls socket 1 channel A DIMM1 fault LED signal
                                        wLED_CPU1_CHA_DIMM1_FAULT,       // DOUT28, controls socket 1 channel A DIMM0 fault LED signal
                                        wReserved_1,                     // DOUT27-24, SPARE

                                        // Below is byte2 (sGPIO[23:16]), default value 8'b0000_0000
                                        wReserved_0,                     // DOUT23-20, SPARE
                                        wLED_CPU0_CHF_DIMM2_FAULT,       // DOUT19, controls socket 0 channel F DIMM1 fault LED signal
                                        wLED_CPU0_CHF_DIMM1_FAULT,       // DOUT18, controls socket 0 channel F DIMM0 fault LED signal
                                        wLED_CPU0_CHE_DIMM2_FAULT,       // DOUT17, controls socket 0 channel E DIMM1 fault LED signal
                                        wLED_CPU0_CHE_DIMM1_FAULT,       // DOUT16, controls socket 0 channel E DIMM0 fault LED signal

                                        // Below is byte1 (sGPIO[15:8]), default value 8'b0000_0000 
                                        wLED_CPU0_CHD_DIMM2_FAULT,       // DOUT15, controls socket 0 channel D DIMM1 fault LED signal
                                        wLED_CPU0_CHD_DIMM1_FAULT,       // DOUT14, controls socket 0 channel D DIMM0 fault LED signal
                                        wLED_CPU0_CHC_DIMM2_FAULT,       // DOUT13, controls socket 0 channel C DIMM1 fault LED signal
                                        wLED_CPU0_CHC_DIMM1_FAULT,       // DOUT12, controls socket 0 channel C DIMM0 fault LED signal
                                        wLED_CPU0_CHB_DIMM2_FAULT,       // DOUT11, controls socket 0 channel B DIMM1 fault LED signal
                                        wLED_CPU0_CHB_DIMM1_FAULT,       // DOUT10, controls socket 0 channel B DIMM0 fault LED signal
                                        wLED_CPU0_CHA_DIMM2_FAULT,       // DOUT 9, controls socket 0 channel A DIMM1 fault LED signal
                                        wLED_CPU0_CHA_DIMM1_FAULT,       // DOUT 8, controls socket 0 channel A DIMM0 fault LED signal

                                        // Below is byte0 (sGPIO[7:0]), default value 8'b0000_0000
                                        wBIOS_POST_CODE_LED_7,           // DOUT 7, controls check point postcode bit 7
                                        wBIOS_POST_CODE_LED_6,           // DOUT 6, controls check point postcode bit 6
                                        wBIOS_POST_CODE_LED_5,           // DOUT 5, controls check point postcode bit 5
                                        wBIOS_POST_CODE_LED_4,           // DOUT 4, controls check point postcode bit 4
                                        wBIOS_POST_CODE_LED_3,           // DOUT 3, controls check point postcode bit 3
                                        wBIOS_POST_CODE_LED_2,           // DOUT 2, controls check point postcode bit 2
                                        wBIOS_POST_CODE_LED_1,           // DOUT 1, controls check point postcode bit 1
                                        wBIOS_POST_CODE_LED_0            // DOUT 0, controls check point postcode bit 0
                })
    );
	

ngsx #(
        .IN_BYTE_REGS(2),
        .OUT_BYTE_REGS(2),
        .RST_VALUE_IN(16'b0000_0000_0000_0000),
	//RESET VALUE FOR DATA COME FROM PFR
        .RST_VALUE_OUT(16'b0000_0011_0000_0000)
	//RESET VALUE FOR DATA GO TO PFR
     
    ) pfr_sgpio
    (
        .iRst_n(Reset_sGPIO_PFR_N),
        .iClk(SGPIO_PFR_CLK),
        .iLoad(SGPIO_PFR_LD_N),
        .iSData(SGPIO_PFR_DOUT),        // Serial data input (driven from sGPIO master)
        .iPData({                       // SCM FPGA to PFR
                                        // Below is byte1 (sGPIO[15:8]), default value 8'b0000_0011
                                        6'b0,                       // iPData 15-10, SPARE
                                        wFM_CPU1_SKTOCC_LVT3_PLD_N, // iPData 9, indicates if CPU1 is populated
                                        wFM_CPU0_SKTOCC_LVT3_PLD_N, // iPData 8, indicates if CPU0 is populated

                                        // Below is byte0 (sGPIO[7:0]), default value 8'b0000_0000
                                        wPWRGD_CPU0_LVC3,           // iPData 7, indicates CPU Powergood
                                        1'b0,                       // iPData 6, indicates RSU IP hide done
                                        wFM_BOARD_SKU_ID0,          // iPData 5, indicates board SKU ID0
                                        wFM_BOARD_SKU_ID1,          // iPData 4, indicates board SKU ID1
                                        wFM_BOARD_SKU_ID2,          // iPData 3, indicates board SKU ID2
                                        wFM_BOARD_SKU_ID3,          // iPData 2, indicates board SKU ID3
                                        wFM_BOARD_SKU_ID4,          // iPData 1, indicates board SKU ID4
                                        wFM_BOARD_SKU_ID5           // iPData 0, indicates board SKU ID5
                }),
        .oSData(SGPIO_PFR_DIN_R),
        .oPData({                       // PFR to SCM FPGA
                                        // Below is byte1 (sGPIO[15:8]), default value 8'b0000_0000
                                        wPFR_RSVD_15_9,             // oPData15-9, SPARE
                                        wSCM_CPLD_UPDATE_HIDE,      // oPData 8, hides SCM FPGA RSU IP

                                        // Below is byte0 (sGPIO[7:0]), default value 8'b0000_0000
                                        wPFR_POST_CODE_LED_0,       // oPData 7, indicates PFR Postcode bit 7
                                        wPFR_POST_CODE_LED_1,       // oPData 6, indicates PFR Postcode bit 6
                                        wPFR_POST_CODE_LED_2,       // oPData 5, indicates PFR Postcode bit 5
                                        wPFR_POST_CODE_LED_3,       // oPData 4, indicates PFR Postcode bit 4
                                        wPFR_POST_CODE_LED_4,       // oPData 3, indicates PFR Postcode bit 3
                                        wPFR_POST_CODE_LED_5,       // oPData 2, indicates PFR Postcode bit 2
                                        wPFR_POST_CODE_LED_6,       // oPData 1, indicates PFR Postcode bit 1
                                        wPFR_POST_CODE_LED_7        // oPData 0, indicates PFR Postcode bit 0
                })
    );


assign     FM_HPFR_IN                        =   1'bz;
assign     FM_LEGACY                         =   1'bz;
assign     FM_HPFR_ACTIVE                    =   1'bz;
assign     HPM_STBY_RST_N                    =   wFM_BMC_INIT_DONE;

assign          FM_TTK_SPI_EN_RJC_N_IN                   =   FM_TTK_SPI_EN_RJC_N;
assign          PFR_DEBUG_JUMPER_RJC_N_IN                =   PFR_DEBUG_JUMPER_RJC_N;
assign          PFR_FORCE_RECOVERY_RJC_N_IN              =   PFR_FORCE_RECOVERY_RJC_N;	

assign          FM_TTK_SPI_EN_RJC_N                  =   FM_TTK_SPI_EN_RJC_N_Override      ? FM_TTK_SPI_EN_RJC_N_Value:1'bz;
assign          PFR_DEBUG_JUMPER_RJC_N                =   PFR_DEBUG_JUMPER_RJC_N_Override  ?PFR_DEBUG_JUMPER_RJC_N_Value:1'bz;
assign          PFR_FORCE_RECOVERY_RJC_N              =   PFR_FORCE_RECOVERY_RJC_N_Override?PFR_FORCE_RECOVERY_RJC_N_Value:1'bz;	

assign          FM_PLT_BMC_THERMTRIP_N                =   wH_CPU0_THERMTRIP_LVC1_N && wH_CPU1_THERMTRIP_LVC1_N && wH_CPU0_MEMTRIP_LVC1_N && wH_CPU1_MEMTRIP_LVC1_N ? 1'b1 : 1'b0;
assign          H_CPU0_CATERR_RMCA_LVC3_N             =   1'bz;
assign          H_CPU1_CATERR_RMCA_LVC3_N             =   1'bz;

assign H_CPU0_ERR0_LVC3_N     = wH_CPU0_ERR0_LVC1_N && wH_CPU1_ERR0_LVT1_N;
assign H_CPU0_ERR1_LVC3_N     = wH_CPU0_ERR1_LVC1_N && wH_CPU1_ERR1_LVT1_N;
assign H_CPU0_ERR2_LVC3_N     = wH_CPU0_ERR2_LVC1_N && wH_CPU1_ERR2_LVT1_N;
assign FM_CPU1_ERR0_LVT3_N    = wH_CPU1_ERR0_LVT1_N;
assign FM_CPU1_ERR1_LVT3_N    = wH_CPU1_ERR1_LVT1_N;
assign FM_CPU1_ERR2_LVT3_N    = wH_CPU1_ERR2_LVT1_N;
assign PWRGD_CPU0_LVC3        = wPWRGD_CPU0_LVC3;
assign FM_FORCE_BMC_UPDATE_CONTROL = wFM_VAL_DBG_JUMPER_EN ? (bmc_force_update_sel ? 1'bZ : 1'b0) : 1'b0;
	
endmodule
